Refractory metals and refractory metal silicides have become the material of choice for interconnecting large numbers of conductive structures. These materials possess low resistivity characteristics normally associated with metals such as aluminum or copper, without providing the manufacturing challenges inherent in these materials (heat sensitivity in the case of aluminum, patterning difficulties in the case of copper). In the prior art, it is generally known to form silicide electrodes on silicon diffusion regions by depositing the refractory metal layer on the substrate, heating the metal to form silicide regions over the exposed silicon regions, and treating the substrate in a wet etchant to remove the unreacted refractory metal.
The above method presents difficulties when adopted for use in shallow junction technologies. The phrase "shallow junctions" or "shallow diffusions" refers to diffusion regions that extend a very small distance (i.e., less than 0.5 microns) into the surface of the silicon substrate. These shallow junction regions make the resulting device characteristics less susceptible to variation due to shorter channel lengths. The above-described silicide forming method may consume up to several tenths of a micron of the underlaying silicon in forming the silicide. This consumption has the effect of greatly reducing the effective dopant concentration at the silicide/diffusion interface, resulting in an increase in the extrinsic resistance of the source/drain electrodes, and in extreme cases could degrade the diode character of the junctions. This in turn reduces the switching speed of the device.
Several solutions have been suggested to remedy this problem. One method is to co-deposit the refractory metal with silicon, such that upon annealing a lesser amount of the junction silicon will be consumed. See for example U.S. Pat. No. 4,663,191, entitled "Salicide Process For Forming Low Sheet Resistance Doped Silicon Junctions," issued 5/5/87 to Choi et al and assigned to the assignee of the invention. Another technique is to provide additional silicon on top of the junction regions. In an article by Reith et al, entitled "Controlled Ohmic Contact and Planarization For Very Shallow Junction Structures," IBM Technical Disclosure Bulletin, Vol. 20, No. 9, February 1978, pp. 3480-3483, silicon added to an aluminum deposition diffuses to the surface of an exposed dopant region. After the aluminum is removed, platinum is deposited and sintered to form platinum silicide. During the sintering cycle, all of the deposited silicon is consumed to prevent consumption of the underlaying shallow junction region. In U.S. Pat. No. 3,375,418, entitled "S-M-S Device With Partial Semiconducting Layers," a thin layer of doped epitaxial silicon is formed over an exposed portion of a silicon substrate by silicon reduction of SiCl4 in H2 at 1200.degree. C. MoSi2 is subsequently deposited over the entire structure, to contact the underlaying silicon through the doped epitaxy. In U.S. Pat. No. 3,753,774, entitled "Method For Making An Intermetallic Contact To A Semiconductor Device," doped silicon is deposited over exposed silicon regions, and platinum is then deposited and sintered to form a platinum silicide contact. In an article by Tsang entitled "Forming Thick Metal Silicide For Contact Barrier," IBM Technical Disclosure Bulletin, Vol. 19, No. 9, February 1977, pp. 3383-3385, a blanket layer of silicon is deposited over a masked substrate, and the silicon is removed from all areas except over the portion of the substrate exposed through the mask. Then a blanket layer of refractory metal is deposited and sintered, such that a silicide is formed over the exposed silicon region.
In the present invention, the goal is to provide an electrically conducting bridge contact between silicon regions laterally separated by a narrow dielectric without providing such a contact between regions laterally separated by a wider dielectric. A specific application of such a process is to form a bridge contact between a polysilicon-filled trench and an adjacent silicon diffusion region, without also bridging to other silicon regions such as the exposed surface of a gate electrode. The general memory cell structure upon which such a process is carried out is shown and described in U.S. Pat. No. 4,688,063, entitled "Dynamic RAM Cell With MOS Trench Capacitor in CMOS." In this patent, the connection between the poly-filled trench and the source diffusion of the adjacent transfer gate FET is formed by depositing and etching a conductive polysilicon layer that bridges over the dielectric separating the two regions. In the above-cited co-pending U.S. co-pending U.S. patent application Ser. No. 793,518, this contact is formed by growing highly doped selective silicon over the two regions. In the above-cited U.S. patent application Ser. No. 920,471, this contact is formed by a silicide in which the refractory metal is deposited under high temperature conditions to provide a columnar grain structure that promotes selective silicide formation. In an article by Choi et al, entitled "CMOS Process For Titanium Salicide Bridging Of A Trench And Simultaneously Allowing For True Gate Isolation," IBM Technical Disclosure Bulletin, Vol. 29, No. 3, August 1986 pp. 1037-1038, a layer of refractory metal is deposited over the entire substrate. Since during the course of deposition the refractory metal is thinner over the gate sidewalls than it is over the remaining portions of the substrate, a subsequent isotropic etch can remove the refractory metal from the gate sidewalls to prevent undesired bridging during a subsequent sintering cycle that forms the desired bridge contact. See also U.S. Pat. No. 4,333,099 (a layer of polysilicon is deposited over a substrate having differentially-doped regions separated by a dielectric, and refractory metal ions are implanted and sintered to form a silicide at that portion of the poly line that provides a P-N junction) and U.S. Pat. No. 4,374,700 (a laterally-extending notch is formed in a dielectric that vertically separates a gate-level interconnecting poly from a diffused region, and a layer of poly is deposited and etched to fill the groove and thus provide a source of silicon during a subsequent refractory metal deposit/sinter cycle that forms a silicide interconnecting the two regions).
Several difficulties are presented by the above art. If a layer of polysilicon is used to form the bridge contact, an additional masking step is required for definition. Since each masking step materially adds to the total cost of the fabrication process, this additional masking step is to be avoided. Moreover, the attendant alignment requirements would materially increase the area required to build the cell. If doped selective silicon is used, the dopant may diffuse out of the silicon bridge to alter the conductivity characteristics of the underlaying silicon regions. This is a particularly egregious concern when applied to differentially doped diffusion regions. If reliance is placed on the thickness of the refractory metal as-deposited, differences in thickness will result in undesired bridging. Finally, it has been found that when the refractory metal is simply deposited and sintered, silicon will up diffuse and be consumed during the silicide reaction. As a result, the upper surface of the resulting silicide will sink below the level of the refractory metal as-deposited. While in ordinary applications this "thinning" is not a problem, in the bridge contact application of the invention it results in random bridge contact fails across the wafer.
Accordingly, there is a need in the art for a bridge-forming process that avoids the problems associated with the above-described methods.